1. Field of the Invention
This disclosure generally relates to circuits and techniques for synchronizing signals from different clock domains. More specifically, this disclosure relates to circuits and techniques that resolve metastability issues while synchronizing signals.
2. Related Art
Clock signals are often distributed globally over an entire integrated circuit. However, as clock frequencies and the number of transistors on an integrated circuit continue to increase, implementing such global clock signals becomes increasingly difficult. Moreover, integrated circuits commonly contain different functional blocks that operate at different speeds. Consequently, many integrated circuits include multiple timing domains. In such integrated circuits, large numbers of synchronizing circuits (“synchronizers”) are often used to interface the different timing domains.
Unfortunately, synchronizer performance does not scale at the same rate as logic-gate performance for deep sub-micron technologies. Furthermore, design criteria for data flip-flops can favor choosing circuit topologies and device sizes that negatively affect synchronizer robustness. For instance, synchronizers that are based on standard data-path flip-flops that strive to minimize data-path delay have become a poor choice for synchronizer use.
Hence, what is needed are synchronization techniques and circuits that facilitate synchronizing across different clock domains without the above-described problems.